Integrated circuits having transistors in close proximity to each other can often exhibit unintended current leakage between adjacent transistors. As a result, various isolation techniques have been developed to reduce such leakage currents.
Shallow trench isolation (STI) is one conventional approach frequently used to reduce leakage currents for integrated circuits having nominal feature sizes approximately equal to or less than 90 nm. STI entails the creation of a trench between adjacent transistors which is then filled with a dielectric material. The dielectric material (for example, silicon dioxide) provides a barrier which impedes the flow of leakage current between the transistors on opposite sides of the trench.
Unfortunately, the introduction of STI trenches can cause unintended stress on the channels of adjacent transistors. Such STI stress is difficult to model and complicates circuit design. For example, STI stress can depend on the channel type, doping level, width, and length of adjacent transistors, as well as the spacing between the channel and the trench and the spacing between additional trenches.
This stress is generally most pronounced in low voltage transistors (e.g., transistors having an operating voltage in the range of approximately 1.2 volts to 3.3 volts). In such low voltage transistors, STI stress can cause reduced electron mobility and increased hole mobility, resulting in slightly enhanced PMOS performance and significantly degraded NMOS performance. The net effect of such changes is slower performance of integrated circuits (for example, CMOS circuits).
For low voltage transistors, such stress effects can be reduced by lining the STI trench with silicon nitride. Unfortunately, such configurations are generally only suitable for low voltage applications. The introduction of the silicon nitride liner can reduce the performance of high voltage transistors, such as flash memory cells and circuitry that supports flash operation or transistors used at input/output pins, and/or having an operating voltage in the range of approximately 5 volts and higher.
For example, the introduction of a silicon nitride liner can interfere with data retention of adjacent flash memory cells. Because silicon nitride tends to absorb hydrogen, it can interfere with the injection and retention of hot electrons with respect to the floating gates of flash memory cells. The silicon nitride layer can also interfere with the growth of additional silicon dioxide in the corners of STI trenches which may be desired to further round the corners in order to provide more uniform electric field distribution.
As a result, conventional STI techniques are generally unsatisfactory for applications where low voltage and high voltage transistors are embedded within a single integrated circuit. Integrated circuits used in programmable logic devices (PLDs) may include high voltage flash memory cells embedded with low voltage transistors in a single integrated circuit. Accordingly, the use of STI trenches in such devices without a silicon nitride liner can increase stress effects on low voltage transistors, but the use of an additional silicon nitride liner can reduce performance of high voltage transistors. Moreover, the creation of a separate high voltage trench after the creation of a low voltage trench on the same substrate can unduly increase manufacturing and design costs.
As a result, there is a need for an improved STI implementation that reduces the disadvantages described above when applied to integrated circuits that include both high voltage and low voltage transistors.